Electronic devices include a wide variety of processors such as application specific integrated circuits (ASIC), digital signal processors (DSP), and microprocessors that use memory devices to store and retrieve information, for example. Very large scale integration (VLSI) circuits (e.g., on the scale of billions of transistors) often include multiple processors that each access and process information that is stored in memory devices that are shared by the multiple processors. The shared memory devices often include memory cells (e.g., bitcells) having multiple ports (e.g., multiport memories) so that the memory devices (and the information stored therein) can be accessed more quickly.
However, implementing multiport memories using space and/or time multiplexing typically requires a greater amount a layout space, increased power, decreased bandwidth, and/or combinations thereof. Space-multiplexing multiport memories, for example, are arranged using a multiplexor that is arranged to receive requests for first and second ports and to alternate sending the request to a memory. Time-multiplexing multiport memories, for example, are arranged using first and second memories that are arranged to respectively receive requests for first and second memories and a multiplexor that is arranged to alternate output the output of each of the first and second memories.
The space-multiplexing approach typically entails using a larger bitcell (e.g., using eight or more-transistors). The (layout) area of each multiport bitcell typically increases exponentially with the number of ports in the bitcell, which results in exponentially greater space requirements for greater numbers of ports in a bitcell. Space-multiplexing typically allows the multiport memory to run at frequencies close to that of a single-port memory. Thus, space-multiplexed memories often use twice the area of, offer similar performance to, and consume twice the power of a single-port memory.
The time-multiplexing approach includes using single-port memories that are coupled to arbitration and priority sequencing logic to avoid bank contentions. Individual port requests for a single-port memory are prioritized and are sequentially sent in time to the single-port memories. The serialization of the individual port requests results in lower frequencies of operation and higher cycle latencies since the single-port memories are accessed sequentially in time. Multiport memories using time-multiplexing typically have a layout area that is comparable to the size of the layout area of single port. Thus, time-multiplexed memories often use a similar amount of area as, offer half the performance of, and consume a similar amount of the power of a single-port memory.
A third approach for implementing multiport memories provides using first and second inputs ports as well as using first and second output ports for a single bitcell such as an “8T” (eight-transistor) bitcell. The multiple-input and multiple-output memories often use twice the area of, offer less performance than, and consume more power than a single-port memory.